The present invention relates to electroplating both sides of a workpiece in the form of a substantially flat, electrically insulative substrate having electrically interconnected circuit patterns on a pair of opposed major surfaces. More particularly, the present invention relates to a method for electroplating at least one metal or metal alloy layer on electrically conductive patterns on both surfaces of a circuit board substrate utilized for mounting and providing electrical connections to a semiconductor integrated circuit (IC) die or chip, as in ball grid array (BGA) device packages.
Electrical circuit boards and similar type components comprising complex, electrically interconnected circuit patterns formed on opposite sides of a planar substrate enjoy widespread utility in the manufacture of electrical and electronic components and devices. For example, an increasingly important aspect of semiconductor integrated circuit (IC) manufacturing technology is mounting of the semiconductor IC die or chip to an appropriate dual-sided substrate as part of a process for forming encapsulated device packages. Frequently, this requires providing the IC chip or die with as many input/output (xe2x80x9cI/Oxe2x80x9d) terminals as is feasible. As a consequence of the requirement for a large number of terminals to be formed on a limited amount of substrate surface, so-called xe2x80x9cball grid arrayxe2x80x9d (xe2x80x9cBGAxe2x80x9d) structures and bonding techniques have been developed in order to provide high areal density interconnections between the IC package and, e.g., a larger substrate.
A typical, encapsulated BGA type semiconductor IC device package 1 is shown in schematic, cross-sectional view in FIG. 1. According to such BGA type packaging, an IC die or chip 2 is mounted on a patterned, upper solder mask layer 3U formed on the upper major surface 4U of a dual-sided substrate 4, i.e., a dual-sided printed circuit board (xe2x80x9cPCBxe2x80x9d) or a ceramic or composite material circuit board (xe2x80x9cCCBxe2x80x9d) having an upper circuit pattern 5U formed thereon. A plurality of electrical connections 6 comprising fine electrical wires, typically of gold (Au), are connected, as by wire bonding, between the upper surface 2U of the IC die or chip 2 and a plurality of electrical bonding pad areas 7B (also termed xe2x80x9cbond fingersxe2x80x9d) of the upper circuit pattern 5U exposed through a plurality of openings 3xe2x80x2 selectively formed in solder mask layer 3U. Each of the electrically conductive traces or lines forming upper circuit pattern 5U is electrically connected by means of an electrically conductive plug or via 7V filling a through-hole 8 extending through the thickness of substrate 4, to at least one electrically conductive trace or line of a lower circuit pattern 5L formed on the lower major surface 4L of the substrate. A plurality of generally circularly-shaped xe2x80x9cball land areasxe2x80x9d 7L are exposed through openings 3xe2x80x3 selectively formed in lower solder mask layer 3L overlying substrate lower major surface 4L for accommodating therein a spaced-apart plurality of spherically-shaped electrical conductors 9 formed of a solder material and constituting a two-dimensional ball grid array (BGA). Finally, BGA package 1 includes a layer of molding material 10 encapsulating at least the IC die or chip 2.
According to BGA methodology, the device package with its spherically-shaped BGA solder balls or bumps is then mated with a corresponding ball grid array (BGA) or bonding pad array on a substrate surface. Once mated, the solder balls or bumps of the IC device package and the corresponding solder balls or bumps or bonding pads of the substrate are heated to effect reflow and mutual bonding, whereby each solder ball or bump forms a bond between the IC device package and the substrate. As a consequence, each bonded combination functions as both an electrical and physical contact.
A variant of the above BGA bonding technology, known as xe2x80x9ccontrolled collapse chip connectionxe2x80x9d, or xe2x80x9cC4xe2x80x9d, is particularly useful in applications having a very high density of electrical interconnections. According to C4 methodology, electrically conductive balls or bumps comprising a solder material are formed on the IC device package, as well as on the mating surface of the substrate. Bonding between the two sets of solder balls or bumps is effected by application of heat and mechanical pressure to the IC device package and the substrate. The application of heat causes both sets of solder-based balls or bumps to reflow, thereby providing physical and ohmic electrical connection therebetween, while the applied mechanical pressure causes the mated pairs of solder-based balls or bumps to at least partially collapse, creating a xe2x80x9cpancakexe2x80x9d shape which advantageously reduces interconnection length and resistance.
An essential feature of the above-described BGA fabrication methodology is the formation of suitable dual-sided substrates 4 having the requisite electrically interconnected circuit patterns 5U, 5L formed on the opposing major surfaces 4U, 4L, wherein the circuit patterns are provided with one or more plated layers for minimizing corrosion due to environmental factors, etc, and for facilitating wetting and adhesion of solder-type contact materials thereto. However, the continuing increase in complexity of the IC chip or die 2 has necessitated a parallel increase in the number of I/O connections required to be made to the IC chip or die. The increase in IC complexity has necessitated a parallel increase in the number and complexity of the requisite electrically conductive traces constituting the upper and lower circuit patterns formed on the substrate, which increase in number and complexity has in turn resulted in a substantial decrease in the inter-trace spacings.
According to conventional methodologies for manufacturing dual-sided circuit boards suitable for use in BGA type packaging applications, multi-trace electrically conductive patterns, typically of copper (Cu) or a Cu-based alloy, are formed, as by conventional techniques, on both major surfaces of a substrate comprised of at least one electrically insulative material selected from polymers, ceramics, glasses, resins, laminates and composites thereof, e.g., epoxy resin-fiberglass composites, and electrically interconnected by means of a plurality electrically conductive via plugs filling through-holes extending between the opposing major surfaces.
FIG. 2A illustrates, in plan view, a corner portion of the upper major surface 4U of a dual-sided substrate 4, wherein each of the individual traces 5TU of upper circuit pattern 5U is shown as extending from the interior portion of upper major surface 4U, where bond fingers 7B are located, to the periphery thereof, where conductive via plugs 7V are formed for electrical interconnection with the lower circuit pattern 4L (which is not necessarily similarly configured). The thus-formed, electrically interconnected upper and lower circuit patterns 5U and 5L are then subjected to a plating process, conventionally electroplating, for depositing thereon a layer or layer system which provides corrosion resistance and facilitates low ohmic resistance bonding of solder-based electrical conductors thereto. Typically, thin layers of Ni and Au are sequentially electroplated over the Cu or Cu-based circuit patterns 5U, 5L for this purpose. According to conventional electroplating processes, at least one electrically conductive tie bar 11 having several lateral extensions 11L, 11R, etc., is formed on at least one of the upper or lower major surfaces (4U or 4L) and in electrical contact with each of the conductive traces on that surface, thereby providing a common electrical contact for connection to a source of electroplating potential, whereby each of the conductive traces 5TU and 5TL of the upper and lower major surfaces 5U and 5L, respectively, are then able to be simultaneously electroplated. The electrical connections between the various conductive traces and tie bar 11 and its several extensions 11L, 11R, etc., are severed after completion of the electroplating.
While the use of electrically tie bars for facilitating simultaneous electroplating of circuit patterns has been generally useful according to prior practices, as a consequence of the increased densification of the traces forming the circuit patterns as required by the progressive increase in IC complexity, the remaining, or free space (or xe2x80x9creal estatexe2x80x9d) on the major surfaces 5U and 5L of the substrate has been progressively reduced to where it currently is at a premium. Stated somewhat differently, trace densification of the circuit patterns has reached a state where the tie bar 11 and its associated extensions 11L, 11R, etc., disadvantageously and deleteriously occupy precious routing space on the substrate surface needed for the additional traces, vias, etc., required by the increased amount of I/O connections to be made to the IC chip or die. Moreover, the presence of the tie bar(s) and associated extensions disadvantageously decreases the signal-to-noise ratio (xe2x80x9cSNRxe2x80x9d) of the device package, and the need to sever the electrical connections between the tie bar and the conductive traces subsequent to electroplating adds additional steps and complexity to the overall substrate preparation process.
FIG. 2B illustrates, in plan view, a corner portion of the upper major surface 4U of an alternately configured dual-sided substrate 4 of conventional type, wherein each of the individual traces 5TU of upper circuit pattern 5U includes a separate tie bar portion 11xe2x80x2 for supplying the electrically interconnected upper and lower circuit patterns 5U, 5L with an electrical potential, typically of negative polarity, for cathodically electroplating thereon a layer or layer system (i.e., a plurality of stacked layers) which, inter alia, provides corrosion resistance and facilitates low ohmic resistance bonding of solder-based electrical conductors thereto. However, as in the embodiment illustrated in FIG. 2A, the individual tie bar portions 11xe2x80x2 according to the alternate embodiment disadvantageously occupy precious xe2x80x9creal estatexe2x80x9d on the substrate surface, which xe2x80x9creal estatexe2x80x9d is currently at a premium due to the increased trace densification resulting from the increase in device complexity.
Accordingly, there exists a need for improved methodology for performing simple, reliable, and rapid electroplating of dual-sided circuit board substrates, which methodology eliminates the need for providing electrically conductive tie bars and associated extensions in electrical contact with the individual conductive traces and other features constituting the conductive circuit patterns prior to electroplating, obviates the need to sever the contacts between the traces and the tie bars subsequent to electroplating, and increases the SNR of the completed device packages.
The present invention, wherein a first layer of an electrically conductive material is placed in temporary electrical contact with a first one of the electrically conductive circuit patterns on a first one of the opposed major surfaces of the substrate for facilitating electroplating of the second one of the electrically conductive patterns on the second major surface, the first layer of electrically conductive material is removed, and a second layer of electrically conductive material is placed in temporary electrical contact with the second one of the electrically conductive patterns on the second one of the opposed major surfaces of the substrate for facilitating electroplating of the first major surface, effectively addresses and solves the need for improved methodology for electroplating electrically interconnected circuit patterns on both sides of a dual-sided substrate while obviating any need for provision, and at least partial removal, of an electrically conductive tie bar with associated lateral extensions. The inventive methodology thus results in process simplification while preserving scarce surface area of the substrate major surfaces for formation of additional electrical traces thereon, and advantageously increases the SNR of the completed device package. Further, the methodology provided by the present invention enjoys diverse utility in the manufacture of numerous and various types of electrical and electronic devices and/or components utilizing dual-sided circuit board substrates.
An advantage of the present invention is an improved method for simple, rapid, and reliable electroplating of printed circuit board and other types of dual-sided substrates comprising electrically interconnected, conductive patterns.
Another advantage of the present invention is an improved method of electroplating dual-sided circuit board substrates for use in fabricating ball grid array (BGA) semiconductor IC device packages.
Yet another advantage of the present invention is an improved method for fabricating encapsulated, BGA semiconductor device packages.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are obtained in part by a method of electroplating a dual-sided workpiece, which method comprises the sequential steps of:
(a) providing a workpiece comprising an insulative substrate including first and second opposed major surfaces, with at least one electrically conductive trace formed on each of said first and second major surfaces, the at least one electrically conductive trace on the first major surface being electrically interconnected to the at least one electrically conductive trace on the second major surface;
(b) covering the at least one electrically conductive trace on the first major surface of the substrate with a first layer of electrically conductive material in electrical contact therewith;
(c) applying an electrical potential to the first layer of electrically conductive material to effect electroplating on the at least one electrically conductive trace on the second major surface;
(d) removing the first layer of electrically conductive material from the first major surface of the substrate;
(e) covering the at least one electrically conductive trace on the second major surface with a second layer of electrically conductive material in electrical contact therewith;
(f) applying an electrical potential to the second layer of electrically conductive material to effect electroplating on the at least one electrically conductive trace on the first major surface thereof; and
(g) removing the second layer of electrically conductive material from the second major surface of the substrate.
According to embodiments of the present invention, step (a) comprises providing as the workpiece a dual-sided circuit board comprising a substrate having flat planar first and second opposed major surfaces, wherein each of the first and second opposed major surfaces includes a plurality of spaced-apart electrically conductive traces forming respective first and second circuit patterns on the first and second opposed major surfaces, and the pluralities of electrically conductive traces on the first and second opposed major surfaces are electrically interconnected by a plurality of electrically conductive vias extending through the thickness of the substrate.
According to particular embodiments of the present invention, step (a) comprises providing as the workpiece a substrate wherein the entire surface areas of each of the first and second electrical circuit patterns are exposed; and steps (b) and (e) each comprise covering the entire surface area of a respective one of the first and second electrical circuit patterns.
According to other embodiments of the present invention, step (a) comprises providing as the workpiece a substrate wherein the entire surface area of the first electrical circuit pattern on the first major surface is exposed and only selected portions of the second electrical circuit pattern on the second major surface are exposed; step (b) comprises covering the entire surface area of the first electrical circuit pattern; and step (e) comprises covering only the exposed surface portions of the second electrical circuit pattern.
According to still other embodiments of the present invention, step (a) comprises providing as the workpiece a substrate wherein only selected portions of the surface areas of each of the first and second electrical circuit patterns are exposed; and steps (b) and (c) each comprise covering only the exposed surface portions of the first and second electrical circuit patterns.
According to further embodiments of the present invention, steps (b) and (e) each comprise covering the respective first and second electrical circuit patterns or selected portions thereof by affixing the respective first or second layer of conductive material thereto by means of e.g., a layer of an electrically conductive adhesive, the first and second layers of conductive material being selected from a metal coated insulative sheet and a metal foil; and steps (d) and (g) each comprise removing the respective metal coated insulative sheet or metal foil by stripping away the layer of electrically conductive adhesive from the respective first or second electrical circuit pattern, wherein steps (d) and (g) each further comprise cleaning and rinsing the substrate after stripping away the respective layer of electrically conductive adhesive.
According to preferred embodiments of the present invention, step (a) comprises providing a dual-sided circuit board comprising at least one insulative material selected from the group consisting of polymers, ceramics, glasses, resins, and laminates and composites thereof; and steps (c) and (f) each comprise electroplating at least one metal or metal alloy layer on the at least one electrically conductive trace.
According to another aspect of the present invention, a method of manufacturing an electrical device package comprises:
(a) providing an insulative substrate having substantially planar upper and lower major surfaces, each of the upper and lower major surfaces including thereon a plurality of electrically conductive traces forming respective upper and lower electrical circuit patterns, the traces of the upper electrical circuit pattern being electrically interconnected with the traces of the lower electrical circuit pattern by means of electrically conductive vias extending through the substrate;
(b) applying a layer of an electrically insulative masking material on each of the upper and lower electrical circuit patterns;
(c) selectively removing portions of each layer of masking material to expose selected surface areas of the plurality of electrically conductive traces comprising each of the upper and lower electrical circuit patterns;
(d) covering the exposed surface areas of the upper electrical circuit pattern with a first layer of an electrically conductive material in electrical contact therewith;
(e) contacting at least the lower surface of the substrate with an electroplating bath and applying a cathodic electrical potential to the first layer of electrically conductive material to electroplate at least one metal or metal alloy layer on the exposed surface areas of the lower electrical circuit pattern;
(f) removing the substrate from contact with the electroplating bath and removing the first layer of electrically conductive material from the exposed areas the upper electrical circuit pattern;
(g) covering the exposed surface areas of the lower electrical circuit pattern with a second layer of an electrically conductive material in electrical contact therewith;
(h) contacting the upper surface of the substrate with an electroplating bath and applying a cathodic electrical potential to the second layer of electrically conductive material to electroplate at least one metal or metal alloy layer on the exposed surface areas of the upper electrical circuit pattern; and
(i) removing the substrate from contact with the electroplating bath and removing the second layer of electrically conductive material from the exposed surface areas of the lower electrical circuit pattern.
According to embodiments of the present invention:
step (a) comprises providing an insulative substrate comprised of a material selected from the group consisting of polymers, ceramics, glass, resins, and laminates and composites thereof;
step (b) comprises applying a layer of a solder mask material on each of the upper and lower major surfaces of the substrate and covering the respective upper and lower electrical circuit patterns; and
step (c) comprises selectively removing portions of the solder mask layer from the upper circuit pattern to form a plurality of electrically conductive bonding pad areas and selectively removing portions of the solder mask layer from the lower circuit pattern to form a plurality of areas for accommodating an array of spaced-apart, spherically-shaped electrical conductors.
According to particular embodiments of the present invention, step (a) comprises providing a substrate wherein each of the upper and lower electrical circuit patterns includes a plurality of copper (Cu) or Cu-based traces; steps (e) and (h) each comprise sequentially electroplating a nickel (Ni) layer and a gold (Au) layer on each of the exposed areas of each of the upper and lower electrical circuit patterns; and the method comprises the further steps of:
(j) affixing a spaced-apart, spherically-shaped electrical conductor to each of the plurality of exposed areas of the lower electrical circuit pattern to form a ball grid array (BGA);
(k) mounting a semiconductor integrated circuit (IC) die or chip on the layer of solder mask material on the upper major surface of the substrate;
(l) forming at least one electrical connection between the IC die or chip and at least one of the bonding pad areas of the upper electrical circuit pattern; and
(m) encapsulating at least the IC die or chip in a molding material.
Additional advantages and aspects of the present invention will become apparent to those skilled in the art from the following detailed description, wherein embodiments of the invention are shown and described, simply by way of illustration of the best mode contemplated for practicing the present invention. As will be described, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.